(1) Field of the Invention
The invention relates to silicon-on-insulator (SOI) devices and, more particularly, to a method to form a silicon-controlled rectifier (SCR) SOI device having improved ESD performance.
(2) Description of the Prior Art
At present, the vast majority of integrated circuit products are formed on bulk semiconductor wafers. However, silicon-on-insulator (SOI) wafer-based products are under development as a majority technology for the future. SOI offers the advantages of improved short channel performance, improved isolation, and reduced power supply capability. However, ESD protection of SOI devices remains a significant challenge to manufacturers. One particular category of ESD devices is the silicon-controlled rectifier (SCR). The SCR is commonly used for ESD protection in bulk semiconductor technology. The present invention relates to SCR development in SOI technology.
Referring now to FIG. 1, an example of a prior art SCR device in a bulk semiconductor process is shown. The substrate 2 herein comprises p-type silicon. An n-well region 4 is formed in the substrate 2. Shallow trench isolation regions (STI) 6 are formed in the substrate 2 to define areas for active devices, sometimes called the OD area. Heavily doped regions 8, 10, 12, and 14 are formed in the n-well 4 and p-substrate 2. More particularly, a first n+ region 8 and a first p+ region 10 are formed in the n-well 4, and a second n+ region 12 and a p+ region 14 are formed in the substrate 2. The first n+ and p+ regions 8 and 10 are coupled together to form an ANODE. The second n+ and p+ regions 12 and 14 coupled together to form the CATHODE. This structure forms two bipolar devices, a npn transistor and a pnp transistor, which will conduct current from the anode to the cathode during an ESD event.
Referring now to FIG. 2, a second prior art, bulk semiconductor device is shown. Here, a low voltage trigger, SCR, or LVT-SCR, is shown. The LVT-SCR comprises the same n-well 4 and p-substrate 2 combination used by the SCR of FIG. 1. The first n+ region 8, first p+ region 10, second n+ region 18, and second p+ region 20 are placed in the n-well 4 and the p-substrate 2 as in the SCR. However, an additional n+ region 16 is added at the interface of the n-well 4 and the p-substrate 2. Further, a MOS gate 22 is added between the second n+ 18 and the third n+ 16. This gate is coupled to the cathode. This LVT-SCR configuration adds an NMOS device to the npn and pnp devices of the SCR. The NMOS device reduces the triggering voltage of the SCR device and thereby improves the ESD protection capability.
The SCR and LVT-SCR devices of the prior present several difficulties in integration with a SOI process. In an SOI process, the devices must be formed in a relatively thin silicon layer overlying a buried insulator layer. This buried insulator layer, in turn, overlies the bulk substrate. The presence of the buried insulator layer improves MOS transistor performance, especially for very short channel devices, and reduces substrate coupling issues by providing excellent device-to-device isolation. Typically, the STI regions are formed down to the buried insulator layer such that each active area is completely isolated from other active areas.
However, these characteristics cause several problems for SCR devices formed in an SOI process having STI isolation. First, the presence of the STI regions within the SCR and LVT-SCR devices reduces the lateral heat transfer property during an ESD event. Consequently, the devices fail at a lower energy dissipation level. Second, the STI pull-down impacts both low-current and high-current characteristics and influences the diode leakage characteristics. Third, the thickness of the silicon layer overlying the buried insulator can restrict the formation of the SCR device. If the silicon layer is relatively thin, then the heavily doped (n+ and p+) regions will extend down to the buried insulator layer. In this case, the traditional SCR and LVT-SCR design will not work because the bipolar devices will not function.
Several prior art inventions relate to the ESD performance of SOI devices. U.S. Pat. No. 6,242,763 to Chen et al teaches a silicon-controlled rectifier (SCR) device for a SOI process. The SCR adds an N+/P+ zener diode to the prior SCR to reduce the trigger voltage. U.S. Pat. No. 5,012,317 to Rountre shows a conventional SCR. The STI is found to degrade the SCR-ESD protection by reducing gains of parasitic bipolar devices and by reducing lateral heat transfer. U.S. Pat. No. 5,530,612 to Maloney shows an ESD circuit using biased and terminated PNP transistor chains. U.S. Pat. No. 5,629,544 to Voldman et al reveals a diode device for ESD having silicide film and trench isolation. U.S. Pat. No. 5,949,634 to Yu shows an ESD circuit triggered by a MOS transistor. U.S. Pat. No. 5,945,714 to Yu discloses a related ESD design.